This file documents the GNU make utility, which determines automatically which pieces of a large program need to be recompiled, and issues the commands to recompile them. This is Edition 0. Buying copies from the FSF supports it in developing GNU and promoting software freedom.

The make utility automatically determines which pieces of a large program need to be recompiled, and issues commands to recompile them. This manual describes GNU makewhich was implemented by Richard Stallman and Roland McGrath.

Development since Version 3. GNU make conforms to section 6. Our examples show C programs, since they are most common, but you can use make with any programming language whose compiler can be run with a shell command.

Indeed, make is not limited to programs. You can use it to describe any task where some files must be updated automatically from others whenever the others change.

To prepare to use makeyou must write a file called the makefile that describes the relationships among files in your program and provides commands for updating each file. In a program, typically, the executable file is updated from object files, which are in turn made by compiling source files. Once a suitable makefile exists, each time you change some source files, this simple shell command:.

The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the recipes recorded in the data base. You can provide command line arguments to make to control which files should be recompiled, or how. See How to Run make. If you are new to makeor are looking for a general introduction, read the first few sections of each chapter, skipping the later sections.

In each chapter, the first few sections contain introductory or general information and the later sections contain specialized or technical information. The exception is the second chapter, An Introduction to Makefilesall of which is introductory. If you are familiar with other make programs, see Features of GNU makewhich lists the enhancements GNU make has, and Incompatibilities and Missing Featureswhich explains the few things GNU make lacks that others have.

For a quick summary, see Options SummaryQuick Referenceand Special Targets. Before reporting a bug or trying to fix it yourself, try to isolate it to the smallest possible makefile that reproduces the problem.

Then send us the makefile and the exact results make gave you, including any error or warning messages. When generating this small makefile, be sure to not use any non-free or unusual tools in your recipes: Finally, be sure to explain what you expected to occur; this will help us decide whether the problem was really in the documentation.

Once you have a precise problem you can report it in one of two ways. Either send electronic mail to:. In addition to the information above, please be careful to include the version number of make you are using. Be sure also to include the type of machine and operating system you are using. You need a file called a makefile to tell make what to do.

GNU make

Most often, the makefile tells make how to compile and link a program. In this chapter, we will discuss a simple makefile that describes how to compile and link a text editor which consists of eight C source files and three header files. The makefile can also tell make how to run miscellaneous commands when explicitly asked for example, to remove certain files as a clean-up operation.

To see a more complex example of a makefile, see Complex Makefile. When make recompiles the editor, each changed C source file must be recompiled. If a header file has changed, each C source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file.

Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable editor. Simple MakefilePrevious: A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A prerequisite is a file that is used as input to create the target. A target often depends on several files.

A recipe is an action that make carries out. A recipe may have more than one command, either on the same line or each on its own line. This is an obscurity that catches the unwary. If you prefer to prefix your recipes with a character other than tab, you can set the. Usually a recipe is in a rule with prerequisites and serves to create a target file if any of the prerequisites change.

However, the rule that specifies a recipe for the target need not have prerequisites. A rulethen, explains how and when to remake certain files which are the targets of the particular rule. A rule can also explain how and when to carry out an action.

A makefile may contain other text besides rules, but a simple makefile need only contain rules. Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less. How Make WorksPrevious: Rule IntroductionUp: Here is a straightforward makefile that describes the way an executable file called edit depends on eight object files which, in turn, depend on eight C source and three header files.

In this example, all the C files include defs. See Splitting Long Lines. To use this makefile to delete the executable file and all the object files from the directory, type:. When a target is a file, it needs to be recompiled or relinked if any of its prerequisites change.

In addition, any prerequisites that are themselves automatically generated should be updated first. In this example, edit depends on each of the eight object files; the object file main. A recipe may follow each line that contains a target and prerequisites. These recipes say how to update the target file. A tab character or whatever character is specified by the. Bear in mind that make does not know anything about how the recipes work.

It is up to you to supply recipes that will update the target file properly. All make does is execute the recipe you have specified when the target file needs to be updated. Consequently, make never does anything with it unless you tell it specifically.

Note that this rule not only is not a prerequisite, it also does not have any prerequisites, so the only purpose of the rule is to run the specified recipe. Targets that do not refer to files but are just actions are called phony targets. See Phony Targetsfor information about this kind of target. See Errors in Recipesto see how to cause make to ignore errors from rm or any other command.

Variables SimplifyPrevious: Simple MakefileUp: This is called the default goal. Goals are the targets that make strives ultimately to update. You can override this behavior using the command line see Arguments to Specify the Goals or with the.

In the simple example of the previous section, the default goal is to update the executable program edit ; therefore, we put that rule first. In the example, this rule is for relinking edit ; but before make can fully process this rule, it must process the rules for the files that edit depends on, which in this case are the object files. Each of these files is processed according to its own rule. The recompilation must be done if the source file, or any of the header files named as prerequisites, is more recent than the object file, or if the object file does not exist.

The other rules are processed because their targets appear as prerequisites of the goal. If some other rule is not depended on by the goal or anything it depends on, etc. Before recompiling an object file, make considers updating its prerequisites, the source file and header files. But make would update automatically generated C programs, such as those made by Bison or Yacc, by their own rules at this time. After recompiling whichever object files need it, make decides whether to relink edit.

This must be done if the file edit does not exist, or if any of the object files are newer than it. If an object file was just recompiled, it is now newer than editso edit is relinked.

Thus, if we change the file insert. If we change the file command. How Make WorksUp: In our example, we had to list all the object files twice in the rule for edit repeated here:. Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other.

We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later see How to Use Variables. It is standard practice for every makefile to have a variable named objectsOBJECTSobjsOBJSobjor OBJ which is a list of all object file names. We would define such a variable objects with a line like this in the makefile:.

Combine By PrerequisitePrevious: Variables SimplifyUp: It is not necessary to spell out the recipes for compiling the individual C source files, because make can figure them out: We can therefore omit the recipes from the rules for the object files.

See Using Implicit Rules. Here is the entire example, with both of these changes, and a variable objects as suggested above:. This is how we would write the makefile in actual practice. See Phony Targetsand Errors in Recipes. Because implicit rules are so convenient, they are important. You will see them used frequently. When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible.

In this style of makefile, you group entries by their prerequisites instead of by their targets. Here is what one looks like:. Whether this is better is a matter of taste: Combine By PrerequisiteUp: Compiling a program is not the only thing you might want to write rules for.

Makefiles commonly tell how to do a few other things besides compiling a program: In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations. We would do this:. This prevents make from getting confused by an actual file called clean and causes it to continue in spite of errors from rm.

A rule such as this should not be placed at the beginning of the makefile, because we do not want it to run by default! Thus, in the example makefile, we want the rule for editwhich recompiles the editor, to remain the default goal. The information that tells make how to recompile a system comes from reading a data base called the makefile. Makefile NamesPrevious: Makefiles contain five kinds of things: Rules, variables, and directives are described at length in later chapters.

You cannot use comments within variable references or function calls: Comments within a recipe are passed to the shell, just as with any other recipe text. The shell decides how to interpret it: Within a define directive, comments are not ignored during the definition of the variable, but rather kept intact in the value of the variable.

When the variable is expanded they will either be treated as make comments or as recipe text, depending on the context in which the variable is evaluated. Makefile ContentsUp: GNU make has no limit on the length of a statement line, up to the amount of memory in your computer.

However, it is difficult to read lines which are too long to display without wrapping or scrolling. So, you can format your makefiles for readability by adding newlines into the middle of a statement: By default, when make looks for the makefile, it tries the following names, in order: GNUmakefilemakefile and Makefile. Normally you should call your makefile either makefile or Makefile. We recommend Makefile because it appears prominently near the beginning of a directory listing, right near other important files such as README.

The first name checked, GNUmakefileis not recommended for most makefiles. You should use this name if you have a makefile that is specific to GNU makeand will not be understood by other versions of make. Other make programs look for makefile and Makefilebut not GNUmakefile. If make finds none of these names, it does not use any makefile. Then you must specify a goal with a command argument, and make will attempt to figure out how to remake it using only its built-in implicit rules.

All the makefiles are effectively concatenated in the order specified. MAKEFILES VariablePrevious: Makefile NamesUp: The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this:. If filenames is empty, nothing is included and no error is printed.

Extra spaces are allowed and ignored at the beginning of the line, but the first character must not be a tab or the value of. Whitespace is required between include and the file names, and between file names; extra whitespace is ignored there and at the end of the directive. If the file names contain any variable or function references, they are expanded.

See How to Use Variables. For example, if you have three. When make processes an include directive, it suspends reading of the containing makefile and reads from each listed file in turn. When that is finished, make resumes reading the makefile in which the directive appears. One occasion for using include directives is when several programs, handled by individual makefiles in various directories, need to use a common set of variable definitions see Setting Variables or pattern rules see Defining and Redefining Pattern Rules.

Another such occasion is when you want to generate prerequisites from source files automatically; the prerequisites can be put in a file that is included by the main makefile. This practice is generally cleaner than that of somehow appending the prerequisites to the end of the main makefile as has been traditionally done with other versions of make.

If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched.

Then the following directories if they exist are searched, in this order: If an included makefile cannot be found in any of these directories, a warning message is generated, but it is not an immediately fatal error; processing of the makefile containing the include continues. See How Makefiles Are Remade.

Only after it has tried to find a way to remake a makefile and failed, will make diagnose the missing makefile as a fatal error. If you want make to simply ignore a makefile which does not exist or cannot be remade, with no error message, use the -include directive instead of includelike this:. This acts like include in every way except that there is no error not even a warning if any of the filenames or any prerequisites of any of the filenames do not exist or cannot be remade.

For compatibility with some other make implementations, sinclude is another name for -include. Remaking MakefilesPrevious: If the environment variable MAKEFILES is defined, make considers its value as a list of names separated by whitespace of additional makefiles to be read before the others. This works much like the include directive: In addition, the default goal is never taken from one of these makefiles or any makefile included by them and it is not an error if the files listed in MAKEFILES are not found.

The main use of MAKEFILES is in communication between recursive invocations of make see Recursive Use of make. It usually is not desirable to set the environment variable before a top-level invocation of makebecause it is usually better not to mess with a makefile from outside. However, if you are running make without a specific makefile, a makefile in MAKEFILES can do useful things to help the built-in implicit rules work better, such as defining search paths see Directory Search.

Some users are tempted to set MAKEFILES in the environment automatically on login, and program makefiles to expect this to be done. This is a very bad idea, because such makefiles will fail to work if run by anyone else.

It is much better to write explicit include directives in the makefiles. See Including Other Makefiles. Overriding MakefilesPrevious: MAKEFILES VariableUp: Sometimes makefiles can be remade from other files, such as RCS or SCCS files. If a makefile can be remade from other files, you probably want make to get an up-to-date version of the makefile to read in. To this end, after reading in all makefiles, make will consider each as a goal target and attempt to update it.

If a makefile has a rule which says how to update it found either in that very makefile or in another one or if an implicit rule applies to it see Using Implicit Rulesit will be updated if necessary. After all makefiles have been checked, if any have actually been changed, make starts with a clean slate and reads all the makefiles over again.

It will also attempt to update each of them over again, but normally this will not change them again, since they are already up to date. If you know that one or more of your makefiles cannot be remade and you want to keep make from performing an implicit rule search on them, perhaps for efficiency reasons, you can use any normal method of preventing implicit rule look-up to do so.

For example, you can write an explicit rule with the makefile as the target, and an empty recipe see Using Empty Recipes. If the makefiles specify a double-colon rule to remake a file with a recipe but no prerequisites, that file will always be remade see Double-Colon. In the case of makefiles, a makefile that has a double-colon rule with a recipe but no prerequisites will be remade every time make is run, and then again after make starts over and reads the makefiles in again.

This would cause an infinite loop: So, to avoid this, make will not attempt to remake makefiles which are specified as targets of a double-colon rule with a recipe but no prerequisites. However, if a default makefile does not exist but can be created by running make rules, you probably want the rules to be run so that the makefile can be used. Therefore, if none of the default makefiles exists, make will try to make each of them in the same order in which they are searched for see What Name to Give Your Makefile until it succeeds in making one, or it runs out of names to try.

Note that it is not an error if make cannot find or make any makefile; a makefile is not always necessary. The recipe printed for foo will be the one specified in the updated contents of mfile.

However, on occasion you might actually wish to prevent updating of even the makefiles. You can do this by specifying the makefiles as goals in the command line as well as specifying them as makefiles. The recipe for foo will be the one specified by the existing contents of mfile.

Reading MakefilesPrevious: Remaking MakefilesUp: Sometimes it is useful to have a makefile that is mostly just like another makefile. However, it is invalid for two makefiles to give different recipes for the same target. But there is another way. In the containing makefile the one that wants to include the otheryou can use a match-anything pattern rule to say that to remake any target that cannot be made from the information in the containing makefile, make should look in another makefile.

See Pattern Rulesfor more information on pattern rules. If Makefile provides a rule for updating barmake will apply the rule. And likewise for any other target that GNUmakefile does not say how to make. The rule specifies a prerequisite forceto guarantee that the recipe will be run even if the target file already exists.

We give the force target an empty recipe to prevent make from searching for an implicit rule to build it—otherwise it would apply the same match-anything rule to force itself and create a prerequisite loop! Secondary ExpansionPrevious: Overriding MakefilesUp: GNU make does its work in two distinct phases. During the first phase it reads all the makefiles, included makefiles, etc.

During the second phase, make uses these internal structures to determine what targets will need to be rebuilt and to invoke the rules necessary to do so. Here we will present a summary of the phases in which expansion happens for different constructs within the makefile.

We say that expansion is immediate if it happens during the first phase: We say that expansion is deferred if expansion is not performed immediately. Expansion of a deferred construct is not performed until either the construct appears later in an immediate context, or until the second phase.

You may not be familiar with some of these constructs yet. You can reference this section as you become familiar with them, in later chapters.

The result is stored in the variable named on the left, and that variable becomes a simple variable and will thus be re-evaluated on each reference. Conditional directives are parsed immediately. This means, for example, that automatic variables cannot be used in conditional directives, as automatic variables are not set until the recipe for that rule is invoked. If you need to use automatic variables in a conditional directive you must move the condition into the recipe and use shell conditional syntax instead.

That is, the target and prerequisite sections are expanded immediately, and the recipe used to construct the target is always deferred.

This general rule is true for explicit rules, pattern rules, suffix rules, static pattern rules, and simple prerequisite definitions. Reading MakefilesUp: In the previous section we learned that GNU make works in two distinct phases: GNU make also has the ability to enable a second expansion of the prerequisites only for some or all targets defined in the makefile.

In order for this second expansion to occur, the special target. If that special target is defined then in between the two phases mentioned above, right at the end of the read-in phase, all the prerequisites of the targets defined after the special target are expanded a second time. In most circumstances this secondary expansion will have no effect, since all variable and function references will have been expanded during the initial parsing of the makefiles.

For example, consider this makefile:. Now during the secondary expansion the first word is expanded again but since it contains no variable or function references it remains the value onefilewhile the second word is now a normal reference to the variable TWOVARwhich is expanded to the value twofile. The final result is that there are two prerequisites, onefile and twofile. Obviously, this is not a very interesting case since the same result could more easily have been achieved simply by having both variables appear, unescaped, in the prerequisites list.

One difference becomes apparent if the variables are reset; consider this example:. Here the prerequisite of onefile will be expanded immediately, and resolve to the value topwhile the prerequisite of twofile will not be full expanded until the secondary expansion and yield a value of bottom. This is marginally more exciting, but the true power of this feature only becomes apparent when you discover that secondary expansions always take place within the scope of the automatic variables for that target.

Also, secondary expansion occurs for both explicit and implicit pattern rules. Knowing this, the possible uses for this feature increase dramatically.

This version allows users to specify source files rather than object files, but gives the same resulting prerequisites list as the previous example. The subtleties of using the different automatic variables are described below. The following example will help illustrate these behaviors:.

In the second, they will have values foo. In the third they will have values foo. Rules undergo secondary expansion in makefile order, except that the rule with the recipe is always evaluated last. Rules for secondary expansion of static pattern rules are identical to those for explicit rules, above, with one exception: As make searches for an implicit rule, it substitutes the stem and then performs secondary expansion for every rule with a matching target pattern.

The value of the automatic variables is derived in the same fashion as for static pattern rules. Note that the directory prefix Das described in Implicit Rule Search Algorithmis appended after expansion to all the patterns in the prerequisites list. It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target. The order of rules is not significant, except for determining the default goal: The default goal is the target of the first rule in the first makefile.

If the first rule has multiple targets, only the first target is taken as the default. There are two exceptions: See Defining and Redefining Pattern Rules. See Arguments to Specify the Goals. Rule SyntaxPrevious: Its target is foo. It has one command in the recipe: The recipe starts with a tab to identify it as a recipe. Prerequisite TypesPrevious: Rule ExampleUp: The targets are file names, separated by spaces. Wildcard characters may be used see Using Wildcard Characters in File Names and a name of the form a m represents member m in archive file a see Archive Members as Targets.

Usually there is only one target per rule, but occasionally there is a reason to have more see Multiple Targets in a Rule. The recipe lines start with a tab character or the first character in the value of the. The first recipe line may appear on the line after the prerequisites, with a tab character, or may appear on the same line, with a semicolon. Either way, the effect is the same.

There are other differences in the syntax of recipes. See Writing Recipes in Rules. You may split a long line by inserting a backslash followed by a newline, but this is not required, as make places no limit on the length of a line in a makefile.

A rule tells make two things: The criterion for being out of date is specified in terms of the prerequisiteswhich consist of file names separated by spaces. Wildcards and archive members see Archives are allowed here too. A target is out of date if it does not exist or if it is older than any of the prerequisites by comparison of last-modification times.

The idea is that the contents of the target file are computed based on information in the prerequisites, so if any of the prerequisites changes, the contents of the existing target file are no longer necessarily valid.

How to update is specified by a recipe. Rule SyntaxUp: There are actually two different types of prerequisites understood by GNU make: A normal prerequisite makes two statements: Second, it imposes a dependency relationship: Normally, this is exactly what you want: Occasionally, however, you have a situation where you want to impose a specific ordering on the rules to be invoked without forcing the target to be updated if one of those rules is executed.

In that case, you want to define order-only prerequisites. Order-only prerequisites can be specified by placing a pipe symbol in the prerequisites list: The normal prerequisites section may of course be empty.

Also, you may still declare multiple lines of prerequisites for the same target: Note that if you declare the same file to be both a normal and an order-only prerequisite, the normal prerequisite takes precedence since they have a strict superset of the behavior of an order-only prerequisite.

Consider an example where your targets are to be placed in a separate directory, and that directory might not exist before make is run. One way to manage this is with order-only prerequisites: Directory SearchPrevious: Prerequisite TypesUp: A single file name can specify many files using wildcard characters. If alone, or followed by a slash, it represents your home directory. Wildcard expansion is performed by make automatically in targets and in prerequisites. In recipes, the shell is responsible for wildcard expansion.

In other contexts, wildcard expansion happens only if you request it explicitly with the wildcard function. The special significance of a wildcard character can be turned off by preceding it with a backslash.

Wildcard PitfallPrevious: Wildcards can be used in the recipe of a rule, where they are expanded by the shell. For example, here is a rule to delete all the object files:. Wildcards are also useful in the prerequisites of a rule. This rule uses print as an empty target file; see Empty Target Files to Record Events. However, if you use the value of objects in a target or prerequisite, wildcard expansion will take place there. If you use the value of objects in a recipe, the shell may perform wildcard expansion when the recipe runs.

To set objects to the expansion, instead use:. Wildcard FunctionPrevious: Wildcard ExamplesUp: Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend. Suppose you would like to say that the executable file foo is made from all the object files in the directory, and you write this:.

This is not what you want! Actually it is possible to obtain the desired result with wildcard expansion, but you need more sophisticated techniques, including the wildcard function and string substitution. See The Function wildcard. Microsoft operating systems MS-DOS and MS-Windows use backslashes to separate directories in pathnames, like so:.

This is equivalent to the Unix-style c: When make runs on these systems, it supports backslashes as well as the Unix-style forward slashes in pathnames. However, this support does not include the wildcard expansion, where backslash is a quote character. Therefore, you must use Unix-style slashes in these cases. Wildcard PitfallUp: Wildcard expansion happens automatically in rules. But wildcard expansion does not normally take place when a variable is set, or inside the arguments of a function.

If you want to do wildcard expansion in such places, you need to use the wildcard function, like this:. This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns.

If no existing file name matches a pattern, then that pattern is omitted from the output of the wildcard function. Note that this is different from how unmatched wildcards behave in rules, where they are used verbatim rather than ignored see Wildcard Pitfall. One use of the wildcard function is to get a list of all the C source files in a directory, like this:. Here we have used another function, patsubst.

See Functions for String Substitution and Analysis. Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows:.

This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files. Phony TargetsPrevious: For large systems, it is often desirable to put sources in a separate directory from the binaries.

The directory search features of make facilitate this by searching several directories automatically to find a prerequisite. When you redistribute the files among directories, you do not need to change the individual rules, just the search paths. Selective SearchPrevious: Directory SearchUp: The value of the make variable VPATH specifies aceh forex trading information list of directories that make should search.

Most often, the directories are expected to contain prerequisite files that are not in the current directory; however, make uses VPATH as a search list for both prerequisites and targets of rules. Thus, if a file that is listed as a target or prerequisite does not exist in the current directory, make searches the directories listed in VPATH for a file with that name. If a file is found in one of them, that file may become the prerequisite see below.

Rules may then specify the names of files in the prerequisite list as if they all existed in the current directory. See Writing Recipes with Directory Search. In the VPATH variable, directory names are separated by colons or blanks.

The order in which directories are listed is the order followed by make in its search. On MS-DOS and MS-Windows, semi-colons are used as separators of directory names in VPATHsince the colon can be used in the currency trading courses in mumbai itself, after the drive letter.

Search AlgorithmPrevious: General Forex 0.1 spreadUp: Similar to the VPATH variable, but more selective, is the vpath directive note lower casewhich allows you to specify a search path for a particular class of file names: Thus you can call waiting iphone 5 tmobile certain search directories for one class of file names and other directories or none for other file names.

The search path, directoriesis a list of directories to be searched, separated by colons semi-colons on MS-DOS and MS-Windows or blanks, just like the search path used in the VPATH variable. When a prerequisite fails to exist in the current directory, if the pattern in a vpath directive matches the name of the prerequisite file, then the directories in that directive are searched just like and before the directories in the VPATH variable.

Selective SearchUp: When a prerequisite is found through directory search, regardless of type general or selectivethe pathname located may not be the one that make actually provides you in the prerequisite list. Sometimes the path discovered through directory search is thrown away. The algorithm make uses to decide whether to keep or abandon a path found via directory search is as follows:. Other versions of make use a simpler algorithm: Thus, if the target is rebuilt it is created at the pathname discovered during directory search.

If, in earn money playing games in india, this is the behavior difference between buying a put option and selling a call option want for some or all of your directories, you can use the GPATH variable to indicate this to make.

GPATH has the same syntax and format as VPATH that is, a space- or colon-delimited list of pathnames. If an out-of-date target is found by directory search in a directory that also appears in GPATHthen that pathname is not thrown away. The target is rebuilt using the expanded path. Search AlgorithmUp: When a prerequisite is found in another directory through directory search, this cannot change the recipe of the rule; they will execute as written.

Therefore, you must write the recipe with care so that it will look for the prerequisite in the directory where make finds it. The variable CFLAGS exists so you can specify flags for C compilation by implicit rules; we use it here for consistency so it will affect all C compilations uniformly; see Variables Used by Implicit Rules. Often the prerequisites include header files as well, which you do not want to mention in the recipe. The search through the directories specified in VPATH or with vpath also happens myer chadstone easter trading hours consideration of implicit rules see Using Implicit Rules.

For example, when a file foo. If such a file is lacking in the current directory, the appropriate directories are searched for it. The recipes of implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort. Directory search applies in a special way to libraries used with the linker. You can tell something strange is going on here because the prerequisite is normally the name of a file, and the file name of a library generally looks like lib name.

Although the default set of files to be searched for is lib name. Each word in the value of this variable is a pattern string. The default value for. Force TargetsPrevious: A phony opinions about binary options traders is one that is not really the name of a file; rather it is just a name for a recipe to be executed when you make an explicit request.

There are two reasons to use a phony target: If you write a rule whose recipe will not create the target file, the recipe will be executed every time the target comes up binary options analysis and trading signals franco remaking. Here is an example:. Because the rm command does instaforex kl create a file named cleanprobably no such file will ever exist.

In this example, the clean target will not work properly if a file named clean is ever created in this directory. Since it has no prerequisites, clean would always be considered up to date and its recipe would not be executed. To avoid this problem you can explicitly declare the target to be phony by making it a prerequisite of the special target. PHONY see Special Built-in Target Names as follows:. Phony targets are forex 0.1 spread useful in conjunction with recursive invocations of make see Recursive Use of make.

In this situation the makefile will often contain a variable which lists a number of sub-directories to be built. A simplistic way to handle this is to define one rule with a recipe that loops over the sub-directories, like this:. There are problems with this method, however.

First, any error detected in a sub-make is ignored by this rule, so it will continue to build the rest of the directories even when one fails. This can be overcome by adding shell commands to note the error and exit, but then it will do so even if make is invoked with the -k option, which is unfortunate.

By declaring the sub-directories as. The implicit rule search see Implicit Rules is skipped for. This is why declaring a target as. PHONY is good for performance, even if you are not worried about the actual file existing. A phony target should not be a prerequisite of a real target file; if it is, its recipe will be run every time make goes to update that file.

As long as a phony target is never a prerequisite of a real target, the phony target foreign currency exchange rates in uganda will be executed only when the phony target is a specified goal see Arguments to Specify the Goals. Impact of fed tapering on stock market targets can have prerequisites.

When one directory contains multiple programs, it is most convenient to describe all of the programs in one makefile. Phoniness is not inherited: When one phony target is a prerequisite of another, it serves as a subroutine of the other. Empty TargetsPrevious: Phony TargetsUp: If a rule has no prerequisites or recipe, and the target of the rule is a nonexistent file, then make imagines this target to have been updated whenever its rule is run.

This implies that all targets depending on this one will always have their recipe run. Special TargetsPrevious: Force TargetsUp: The empty target is a variant of the phony target; it is used to hold recipes for an action that you request explicitly from time to time. It does so because one of the commands in the recipe is a touch command to update the target file. When you ask to remake the empty target, the recipe is executed if any prerequisite is more recent than the madison square garden stock certificate in other words, if a prerequisite has changed since the last time you remade the target.

Multiple TargetsPrevious: Empty TargetsUp: The prerequisites of the special target. PHONY are considered to be phony targets. When it is time to consider such a target, make will run its recipe unconditionally, regardless of whether a file with that name exists or what its last-modification time is.

SUFFIXES are the list of suffixes to be used in checking for profitable binary option trading platforms uk rules. See Old-Fashioned Suffix Rules. The recipe specified for.

DEFAULT is used for any target for which no rules are found either explicit rules or implicit rules. DEFAULT recipe is specified, every file mentioned as a prerequisite, but not as a target in a rule, will have that recipe executed on its behalf.

See Implicit Rule Search Algorithm. PRECIOUS depends on are given the following special treatment: See Interrupting or Killing make. Also, if the target is an intermediate file, it will not be deleted after it is no longer needed, as is normally done.

See Chains of Implicit Rules. In this latter respect it overlaps with the. SECONDARY depends on are treated as intermediate files, except that they are never automatically deleted. SECONDARY with no prerequisites causes how to become a chartered financial analyst in india targets to be treated as secondary i.

See Errors in Recipes. If you specify prerequisites for. IGNOREthen make will ignore errors in execution of the recipe for those particular files. IGNORE if any is ignored. If mentioned as a target with no prerequisites.

IGNORE says to ignore errors in execution of recipes for all files. Since this affects every recipe in the makefile, it is not very useful; we recommend you use the more selective ways to ignore errors in specific recipes.

The recipe for the. The high resolution file time stamps of many modern file systems lessen the chance of make incorrectly concluding that a file is up to date. If a file is created by such a command, you should attribution de stock options en anglais it as a prerequisite of.

Due to a limitation of the archive format, archive member time stamps are always low resolution. You need not list archive members as prerequisites of. SILENTthen make will not print the recipe used to remake those particular files before executing them. SILENT says not to print any recipes before executing them.

We recommend you use the more selective ways to silence specific recipes. Simply by being mentioned as a target, this tells make to export all variables to child processes by default. See Communicating Variables to a Sub- make. Any recursively invoked make command will still run recipes in parallel unless its makefile also contains this target. Any prerequisites on this target are ignored.

ONESHELL is mentioned as a target, then when a target is built all lines of the recipe will be given to a single invocation of the shell rather than each line being invoked separately see Recipe Execution. POSIX is mentioned as a target, then the makefile will be parsed and run in POSIX-conforming mode.

This does not mean that only POSIX-conforming makefiles will be accepted: In particular, if this target is mentioned then recipes will be invoked as if the shell had been passed the -e flag: These targets are suffix rules, an obsolete way of defining implicit rules attribution de stock options en anglais a way still widely used.

In principle, any target name could be special in this way if you break it in two and add both pieces to the suffix list. Multiple RulesPrevious: Special TargetsUp: A rule with multiple targets is equivalent identifying trends in stock market writing many rules, each with one target, and all identical aside from that.

The rule contributes the same prerequisites to all the targets also. See Functions fxcm forex options String Substitution and Analysisfor an explanation of the subst function. You cannot do this with multiple targets in an ordinary rule, but you can do it with a static pattern rule. See Static Pattern Rules.

Static PatternPrevious: Multiple TargetsUp: One file can be the target of several rules. All the prerequisites mentioned in all the rules are merged into one list of prerequisites for the target. If the target is older than any prerequisite from any rule, the recipe is executed. There can only be one recipe to be executed for a file. If more than nasdaq traded penny stocks rule gives a recipe for the same file, make uses the last one given and prints an error message.

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This odd behavior is only for compatibility with other implementations of make … you should avoid using it. Occasionally it is useful to have the same target invoke multiple recipes which are defined in different parts of your makefile; you can use double-colon rules see Double-Colon for this. An extra rule with just prerequisites can be used to give a few extra prerequisites to many files at once.

For example, makefiles often have a variable, such as objectscontaining a list of all the compiler output files in the system being made. An easy way to say that all of them must be recompiled if config. This could be inserted or taken out without changing the rules that ayr market livestock specify how to make the object files, making it a convenient form to use if you wish to add the additional prerequisite intermittently.

Another wrinkle is that the additional prerequisites could be specified with a variable that you set with a command line argument to make see Overriding Variables. If none of the explicit rules for a target has a recipe, then make searches for an applicable implicit rule to find one see Using Implicit Rules. Multiple RulesUp: Static pattern rules are rules which specify multiple targets and construct the prerequisite names for each target based on the target name.

They are more general than ordinary attila stockbroker free europe lyrics with multiple targets because the targets do not have to have identical prerequisites. Their prerequisites must be analogousbut not necessarily identical.

Static versus ImplicitPrevious: Static PatternUp: The targets list specifies the targets that the rule applies to. The targets can contain wildcard characters, just like the targets of ordinary rules see Using Wildcard Characters in File Names. The target-pattern and prereq-patterns say how to compute the prerequisites of each target.

Each target is matched against the target-pattern to extract a part of the target name, called the stem. This stem is substituted into each of the prereq-patterns to make the prerequisite names one from each prereq-pattern. The rest of the pattern must match exactly. For example, the target foo. Here is an example, which compiles each of foo.

Each target specified must match the target pattern; a warning is issued for each target that does not. If you have a list of files, only some of which will match the pattern, you can use the filter function to remove non-matching file names see Functions for String Substitution and Analysis:. Static UsageUp: A static pattern rule has much in common with an implicit rule defined as a pattern rule earn extra mlm money online Defining and Redefining Pattern Rules.

Both have a pattern for the target and patterns for constructing the names of prerequisites. The difference is in how make decides when the rule applies. An implicit rule can apply to any target that matches its pattern, but it does apply only when the target has no recipe otherwise specified, and only when the prerequisites can be found.

If more than one implicit rule appears applicable, only one applies; the choice depends on the order of rules. By contrast, a static pattern rule applies to the precise list of targets that you specify in the rule. It cannot apply to any other target and it invariably does apply to each of the targets specified.

Automatic PrerequisitesPrevious: They are handled differently from ordinary rules when the same target appears in more than one rule. Pattern rules with double-colons have an entirely different meaning see Match-Anything Rules. When a target appears in multiple rules, all the rules must be the same type: If they are double your forex account daily, each of them is independent of the others.

If there are no prerequisites for that rule, its recipe is always executed even if the target already exists. This can result in executing none, any, or all of the double-colon rules. Double-colon rules with the same target are in fact completely separate from one another. Each double-colon rule is processed individually, vfx forex system review as rules with different targets are processed.

The double-colon rules for a target are executed in the order they appear in the makefile. However, the cases where double-colon rules really make sense are those forex hartschaumplatten bedrucken the order of executing the recipes would the moneymaker rilo matter.

Double-colon rules are somewhat obscure and not often very useful; they provide a mechanism for cases in which the method used to update a target differs depending on which prerequisite files caused the update, and such cases are rare. Each double-colon rule should specify a recipe; if it does not, an implicit rule will be used if one applies. In the makefile for a program, many of the rules you need to write often say only that some object file depends on some header file. For example, if main.

You need this rule so that make knows that it must remake main. You can see that for a large program you would have to write dozens of such rules in your makefile.

And, you must always be very careful to update the makefile every time you add or remove an include. To avoid this hassle, most modern C compilers can write these rules for you, by looking at the include lines in the source files.

For example, the command:. Note that such a rule constitutes mentioning main. That command would create a file depend containing all the automatically-generated prerequisites; then the makefile could use include to read them in see Include.

In GNU makethe feature of remaking makefiles makes this practice obsolete—you need never tell make explicitly to regenerate the prerequisites, because it always regenerates any makefile that is out of date. The practice we recommend for automatic prerequisite generation is to have one makefile corresponding to each source file.

For each source file name. That way only the source files that have changed need to be rescanned to produce the new prerequisites. Here is the pattern rule to generate a file of prerequisites i.

See Pattern Rulesfor information on defining pattern rules. This omits prerequisites on system header files. See Options Controlling the Preprocessor in Using GNU CCfor details. See Substitution Refsfor full information on substitution references. See How Make Works. Using VariablesPrevious: Forex blueprint system recipe of a rule consists of one or more shell command lines to be executed, one at a time, in the order they appear.

I forex wiki, the result of executing these commands is that the target of the rule is brought up to date.

Makefiles have the unusual property that there are really two distinct syntaxes in one file. Most of the makefile uses make syntax see Writing Makefiles. However, recipes are meant to be interpreted by the shell and so they are written using shell syntax.

The make program does not try to understand shell syntax: Each line in the recipe must start with a tab or the first character in the value of the. Blank lines and lines of just comments may appear among the recipe lines; they are ignored. Variables in RecipesPrevious: Recipe SyntaxUp: One of the few ways in which make does interpret recipes is checking for a backslash just before the newline.

As in normal makefile syntax, a single logical recipe line can be split into multiple physical lines in the makefile by placing a backslash before each newline. A sequence of lines like this is considered a single recipe line, and one instance of the shell will be invoked to run it. Both the backslash and the newline characters are preserved and passed to the shell. Whitespace is never added to the forexpros usd thb. If you specify a different shell in your makefiles it may treat them differently.

This is often the case when passing scripts to languages such as Perl, where extraneous backslashes inside the script can change its meaning or even be a syntax error. One simple way of handling this is to place the quoted string, or even the entire command, into a make variable then use the variable in the recipe. If we rewrite our example above using this method:. If you like, you can also use target-specific variables see Target-specific Variable Values to obtain a tighter correspondence between the variable and the recipe that uses it.

Splitting Recipe LinesUp: The other way in which make processes recipes is by expanding any variable references in them see Basics of Variable References. This occurs after make has finished reading all the makefiles and the target is determined to be out of date; so, the recipes for targets which are not rebuilt are never expanded. Variable and function references in recipes have identical syntax and semantics to references elsewhere in the makefile. They also have the same quoting rules: Normally make prints each line of the recipe before it is executed.

We call this echoing because it gives forex robot live testing appearance that you are typing the lines yourself. Typically you would use this for a command whose only effect is to print something, such as an echo command to indicate progress through the makefile:.

See Summary of Options. This flag is useful for finding out which recipes make thinks are necessary without actually doing them. A rule in the makefile for the special target. SILENT without prerequisites has the same effect see Special Built-in Target Names. When it is time to execute recipes to update a target, they are executed by invoking a new sub-shell for each line of the recipe, unless the.

ONESHELL special target is in effect see Using One Shell In practice, make may take shortcuts that do not affect the results. Then make will invoke one shell to run the entire line, and the shell will execute the statements in sequence. Choosing the ShellPrevious: Sometimes you would prefer that all the lines in the recipe be passed to a single invocation of the shell. There are generally two situations where this is useful: Second, you might want newlines to be included in your recipe command for example perhaps you are using a very different interpreter as your SHELL.

ONESHELL special target appears anywhere in the makefile then all recipe lines for each target will be provided to a single invocation of the shell.

Newlines between recipe lines will be preserved. Subsequent lines will include the special characters in the recipe line when the SHELL is invoked. This feature is intended to allow existing makefiles to add the. ONESHELL special target and still run properly without extensive modifications. Since the special prefix characters are not legal at the beginning of a line in a POSIX shell script this is not a loss in functionality.

For example, this works as expected:. Even with this special feature, however, makefiles with. ONESHELL will behave differently in ways that could be noticeable. For example, normally if any line in the recipe fails, that causes the rule to fail and no more recipe lines are processed. ONESHELL a failure of any but the final recipe line will not be noticed by make. Ultimately you may need to harden your recipe lines to allow them to work with.

Binary options strategies c 5 minute trades ShellUp: The program used as the shell is taken from the variable SHELL. The argument cara deposit instaforex melalui bank mandiri passed to the shell are taken from the variable.

The default value of. Unlike most variables, the variable SHELL is never set from the environment. This is because the SHELL environment variable is used to specify your personal choice of shell program for interactive use.

It would be very bad for personal choices like this to affect the functioning of makefiles. See Variables from the Environment. Furthermore, when you do set SHELL in your makefile that value is not exported in the environment to recipe lines that make invokes.

You can override this behavior by explicitly exporting SHELL see Communicating Variables to a Sub- makeforcing it to be passed in the environment to recipe lines. However, on MS-DOS and MS-Windows the value of SHELL in the environment is used, since on those systems most users do not set this variable, and therefore it is most likely set specifically to be used by make. On MS-DOS, if the setting of SHELL is not suitable for makeyou can set the variable MAKESHELL to the shell that make should use; if set it will be used as the shell instead of the value of SHELL.

On MS-DOS, if SHELL is not set, the value of the variable COMSPEC which is always set is used instead. The processing of lines that set the variable SHELL in Makefiles is different on MS-DOS. The stock shell, command. Therefore, on MS-DOS, make examines the day trading strategies (momentum) for beginners class 4 of 12 of SHELLand changes its behavior based on whether it points to a Vb.net exec stored procedure with parameters or DOS-style shell.

This allows reasonable functionality even if SHELL points to command. If SHELL points to a Unix-style shell, make on MS-DOS additionally checks whether that shell can indeed be found; if not, it ignores the line that sets SHELL. In MS-DOS, GNU make searches for the shell in the following places:. In every directory it examines, make will first look for the specific file sh in the example above. If this is not found, it will also look in that directory for that file with one of the known extensions which identify executable files.

If any of these attempts is successful, the value of SHELL will be set to the full pathname of the shell as found. However, if none of these is found, the value of Binary options pending order will not be changed, and thus the line that sets it will be effectively ignored.

This is so make will only support features specific to a Unix-style shell if such a shell is actually installed on the system where make runs.

Note that this extended search for the shell is limited to the cases where SHELL is set from the Makefile; if it is set in the environment or command line, you are expected to set it to the full pathname of the shell, exactly as things are on Unix.

GNU make knows how to execute several recipes at once. Normally, make will execute only one recipe at a time, waiting for it to finish before executing the next. You can inhibit parallelism in a particular makefile with the. The default number of job slots is one, which means serial execution one thing at a time.

Handling recursive make invocations raises issues for parallel execution. For more information on this, see Communicating Options to a Sub- make.

If a recipe fails is killed by a signal or exits with a nonzero statusand errors are not ignored for that recipe see Errors in Recipesthe remaining recipe lines to remake the same target will not be run. If make terminates for any reason including a signal with child processes running, it waits for them to finish before actually exiting. When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded. Parallel InputPrevious: When running several recipes in parallel the output from each recipe appears as soon as it is generated, with the result that messages from different recipes may be interspersed, sometimes even appearing on the same line.

This can make reading the output very difficult. This option instructs make to save the output from the commands it invokes and print it all once the commands are completed. Additionally, if there are multiple recursive make invocations running in parallel, they will communicate so that only one of them is generating output at a time. There are four levels of granularity when synchronizing output, specified by giving an argument to the option e.

This is the default: Output from each individual line of the recipe is grouped and printed as soon as that line is complete. If a recipe consists of multiple lines, they may be interspersed with lines from other recipes. Output from the entire recipe for each target is grouped and printed once the target is complete.

This is the default if the --output-sync or -O option is given with no argument. Output from each recursive invocation of make is grouped and printed once the recursive invocation is complete.

Regardless of the mode chosen, the total build time will be the same. The only difference is in how the output appears. The difference between them is in how recipes that contain recursive invocations of make are treated see Recursive Use of make.

This ensures output from all real estate investors in mumbai targets built by a given recursive make instance are grouped together, which may make the output easier to understand.

However it also leads to long periods of time during the build where no output is seen, followed by large bursts of output. If you are not watching the build as it proceeds, but instead viewing a log of the build after the fact, this may be the best option for you.

If you input type radio php mysql watching the output, the long gaps of quiet during the build can be frustrating. The recursive make will perform the synchronization for its targets and currency exchange los angeles world trade center output from each will be displayed immediately when it completes.

Be aware that output from recursive lines of the recipe are not synchronized for example if the recursive line prints a message before running makethat message will not be synchronized. For example, many programs that can display colorized output will not do so if they determine they are not writing to a terminal. Parallel OutputUp: Two processes cannot both take input from the same device at the same time. To make sure that only one recipe tries to take input from the terminal at once, make will invalidate the standard input streams of all but one running recipe.

It is unpredictable which recipe will have a valid standard input stream which will come from the terminal, or wherever you redirect the standard input of make. The first recipe run will always get it first, and the first recipe started after that one finishes will get it next, and so on. We will change how this aspect of make works if we find a better alternative. In the mean time, you should not rely on any recipe using standard input at all if you are using the parallel execution feature; but if you are not using this feature, then standard input works normally in all recipes.

After each shell invocation returns, make looks make easy money on fiverr its exit status.

If the shell completed successfully the exit status is zerothe next line in the recipe is executed in a new shell; after the last line is finished, the rule is finished. If there is an error the exit status is nonzeromake gives up on the current rule, and perhaps on all rules. Sometimes the failure of a certain academy of financial trading education limited review line does not indicate a problem.

For example, you may use the mkdir command to ensure that a directory exists. If the directory already exists, mkdir will report an error, but you probably want make to continue regardless. IGNORE has the same effect, if there are no prerequisites. When an error happens that make has not been told to ignore, it implies that the current target cannot be correctly remade, and neither can any other that depends on it either directly or indirectly.

No further recipes will be executed for these targets, since their preconditions have not been achieved. Normally make gives up immediately in this circumstance, returning a nonzero status.

The usual behavior assumes that your purpose is to get the specified targets up to date; once make learns that this is impossible, it might as well report the failure immediately. Usually when a recipe line fails, if it has changed the target file at all, the file is corrupted and cannot be used—or at least it is not completely updated. The situation is just the same as when the shell is killed by a signal; see Interrupts. So generally the right thing to do is to delete the target file if the recipe fails after beginning to change the file.

This is almost always what you want make to do, but it is not historical practice; so for compatibility, you must explicitly request it. If make gets a fatal signal while a shell is executing, it may delete the target file that the recipe was supposed to update. The purpose of deleting the target is to make sure that it is remade from scratch when make is next run.

Suppose you type Ctrl-c while a compiler is running, and it has begun to write an object file foo. The Ctrl-c kills the compiler, resulting in an incomplete file whose last-modification time is newer than the source file foo. But make also receives the Ctrl-c signal and deletes this incomplete file. If make did not do this, the next invocation of make would think that foo.

You can prevent the deletion of a target file in this way by making the special target. PRECIOUS depend on it. Before remaking a target, make checks to see whether it appears on the prerequisites of.

PRECIOUSand thereby decides whether the target should be deleted if a signal happens. Some reasons why you might do this are that the target is updated in some atomic fashion, or exists only to record a modification-time its contents do not matteror must exist at all times to prevent other sorts of trouble. Canned RecipesPrevious: Recursive use of make means using make as a command in a makefile. This technique is useful when you want separate makefiles for various subsystems that compose a larger system.

You can do it by writing this:. You can write recursive make commands just by copying this example, but there are many things to know about how they work and why, and about how the sub- make relates to the top-level make. For your convenience, when GNU make starts after it has processed any -C options it sets the variable CURDIR to the pathname of the current working directory. This value is never touched by make again: The value has the same precedence it would have if it were set in the makefile by default, an environment variable CURDIR will not override this value.

Note that setting this variable has no impact on the operation of make it does not cause make to change its working directory, for example. The value of this variable is the file name with which make was invoked. If you use a special version of make to run the top-level makefile, the same special version will be executed for recursive invocations.

See Instead of Executing the Recipes. This special feature is only enabled if the MAKE variable appears directly in the recipe: The special feature makes this do what you want: Recipe lines containing MAKE are executed normally despite the presence of a flag that causes most recipes not to be run. The usual MAKEFLAGS mechanism passes the flags to the sub- make see Communicating Options to a Sub- makeso your request to touch the files, or print the recipes, is propagated to the subsystem.

MAKE VariableUp: Variable values of the top-level make can be passed to the sub- make through the environment by explicit request. To pass down, or exporta variable, make adds the variable and its value to the environment for running each line of the recipe. The sub- makein turn, uses the environment to initialize its table of variable values.

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Except by explicit request, make exports a variable only if it is either defined in the environment initially or set on the command line, and if its name consists only of letters, numbers, and underscores. Some shells cannot cope with environment variable names consisting of characters other than letters, numbers, and underscores.

The value of the make variable SHELL is not exported. Instead, the value of the SHELL variable from the invoking environment is passed to the sub- make.

You can force make to export its value for SHELL by using the export directive, described below. See Choosing the Shell. The special variable MAKEFLAGS is always exported unless you unexport it. MAKEFILES is exported if you set it to anything. Variables are not normally passed down if they were created by default by make see Variables Used by Implicit Rules. The sub- make will define these for itself. If you want to export specific variables to a sub- makeuse the export directive, like this:.

If you want to prevent a variable from being exported, use the unexport directive, like this:. In both of these forms, the arguments to export and unexport are expanded, and so could be variables or functions which expand to a list of variable names to be un exported.

You may notice that the export and unexport directives work in make in the same way they work in the shell, sh. This tells make that variables which are not explicitly mentioned in an export or unexport directive should be exported. Any variable given in an unexport directive will still not be exported. If you use export by itself to export variables by default, variables whose names contain characters other than alphanumerics and underscores will not be exported unless specifically mentioned in an export directive.

The behavior elicited by an export directive by itself was the default in older versions of GNU make. If your makefiles depend on this behavior and you want to be compatible with old versions of makeyou can write a rule for the special target. This will be ignored by old make s, while the export directive will cause a syntax error.

Likewise, you can use unexport by itself to tell make not to export variables by default. Since this is the default behavior, you would only need to do this if export had been used by itself earlier in an included makefile, perhaps.

You cannot use export and unexport by themselves to have variables exported for some recipes and not for others. The last export or unexport directive that appears by itself determines the behavior for the entire run of make.

As a special feature, the variable MAKELEVEL is changed when it is passed down from level to level. The incrementation happens when make sets up the environment for a recipe. The main use of MAKELEVEL is to test it in a conditional directive see Conditional Parts of Makefiles ; this way you can write a makefile that behaves one way if run recursively and another way if run directly by you.

You can use the variable MAKEFILES to cause all sub- make commands to use additional makefiles. The value of MAKEFILES is a whitespace-separated list of file names. This variable, if defined in the outer-level makefile, is passed down through the environment; then it serves as a list of extra makefiles for the sub- make to read before the usual or specified ones.

See The Variable MAKEFILES. This variable is set up automatically by make to contain the flag letters that make received. As a consequence, every sub- make gets a value for MAKEFLAGS in its environment.

In response, it takes the flags from that value and processes them as if they had been given as arguments. Likewise variables defined on the command line are passed to the sub- make through MAKEFLAGS. If you do not want to pass the other flags down, you must change the value of MAKEFLAGSlike this:.

This is not usually useful to do. However, some systems have a small fixed limit on the size of the environment, and putting so much information into the value of MAKEFLAGS can exceed it.

For strict compliance with POSIX. You probably do not care about this. A similar variable MFLAGS exists also, for historical compatibility. MFLAGS was traditionally used explicitly in the recursive make command, like this:. If you want your makefiles to be compatible with old make programs, use this technique; it will work fine with more modern make versions too.

You simply put a value for MAKEFLAGS in your environment. You can also set MAKEFLAGS in a makefile, to specify additional flags that should also be in effect for that makefile. Note that you cannot use MFLAGS this way. That variable is set only for compatibility; make does not interpret a value you set for it in any way. When make interprets the value of MAKEFLAGS either from the environment or from a makefileit first prepends a hyphen if the value does not already begin with one.

If you do put MAKEFLAGS in your environment, you should be sure not to include any options that will drastically affect the actions of make and undermine the purpose of makefiles and of make itself.

This variable is parsed just before MAKEFLAGSin the same way as MAKEFLAGS. If your makefiles require GNU make anyway then simply use MAKEFLAGS. Empty RecipesPrevious: When the same sequence of commands is useful in making various targets, you can define it as a canned sequence with the define directive, and refer to the canned sequence from the recipes for those targets. The canned sequence is actually a variable, so the name must not conflict with other variable names.

Here run-yacc is the name of the variable being defined; endef marks the end of the definition; the lines in between are the commands. See Defining Multi-Line Variablesfor a complete explanation of define. The first command in this example runs Yacc on the first prerequisite of whichever rule uses the canned sequence. The output file from Yacc is always named y.

To use the canned sequence, substitute the variable into the recipe of a rule. You can substitute it like any other variable see Basics of Variable References. Because variables defined by define are recursively expanded variables, all the variable references you wrote inside the define are expanded now. This is a realistic example, but this particular one is not needed in practice because make has an implicit rule to figure out these commands based on the file names involved see Using Implicit Rules.

In recipe execution, each line of a canned sequence is treated just as if the line appeared on its own in the rule, preceded by a tab. In particular, make invokes a separate sub-shell for each line. For example, using this canned sequence:. But it will echo the following two recipe lines. On the other hand, prefix characters on the recipe line that refers to a canned sequence apply to every line in the sequence.

Canned RecipesUp: It is sometimes useful to define recipes which do nothing. This is done simply by giving a recipe that consists of nothing but whitespace. You could also use a line beginning with a recipe prefix character to define an empty recipe, but this would be confusing because such a line looks empty. You may be wondering why you would want to define a recipe that does nothing. One reason this is useful is to prevent a target from getting implicit recipes from implicit rules or the.

DEFAULT special target; see Implicit Rules and see Defining Last-Resort Default Rules. Empty recipes can also be used to avoid errors for targets that will be created as a side-effect of another recipe: You may be inclined to define empty recipes for targets that are not actual files, but only exist so that their prerequisites can be remade.

However, this is not the best way to do that, because the prerequisites may not be remade properly if the target file actually does exist. See Phony Targetsfor a better way to do this. These values are substituted by explicit request into targets, prerequisites, recipes, and other parts of the makefile.

In some other versions of makevariables are called macros. Variables can represent lists of file names, options to pass to compilers, programs to run, directories to look in for source files, directories to write output in, or anything else you can imagine. However, variable names containing characters other than letters, numbers, and underscores should be considered carefully, as in some shells they cannot be passed through the environment to a sub- make see Communicating Variables to a Sub- make.

Variable names are case-sensitive. It is traditional to use upper case letters in variable names, but we recommend using lower case letters for variable names that serve internal purposes in the makefile, and reserving upper case for parameters that control implicit rules or for parameters that the user should override with command options see Overriding Variables.

A few variables have names that are a single punctuation character or just a few characters. These are the automatic variablesand they have particular specialized uses. Using VariablesUp: Variable references can be used in any context: Here is an example of a common case, where a variable holds the names of all the object files in a program:. A dollar sign followed by a character other than a dollar sign, open-parenthesis or open-brace treats that single character as the variable name.

However, this practice is strongly discouraged, except in the case of the automatic variables see Automatic Variables. There are two ways that a variable in GNU make can have a value; we call them the two flavors of variables.

The two flavors are distinguished in how they are defined and in what they do when expanded. The first flavor of variable is a recursively expanded variable. The value you specify is installed verbatim; if it contains references to other variables, these references are expanded whenever this variable is substituted in the course of expanding some other string. When this happens, it is called recursive expansion. This flavor of variable is the only sort supported by most other versions of make.

It has its advantages and its disadvantages.

An advantage most would say is that:. A major disadvantage is that you cannot append something on the end of a variable, as in. Actually make detects the infinite loop and reports an error. Another disadvantage is that any functions see Functions for Transforming Text referenced in the definition will be executed every time the variable is expanded.

This makes make run slower; worse, it causes the wildcard and shell functions to give unpredictable results because you cannot easily control when they are called, or even how many times. To avoid all the problems and inconveniences of recursively expanded variables, there is another flavor: The value of a simply expanded variable is scanned once and for all, expanding any references to other variables and functions, when the variable is defined.

The actual value of the simply expanded variable is the result of expanding the text that you write. It does not contain any references to other variables; it contains their values as of the time this variable was defined. See The shell Function. This example also shows use of the variable MAKELEVELwhich is changed when it is passed down from level to level.

See Communicating Variables to a Sub- makefor information about MAKELEVEL. Simply expanded variables generally make complicated makefile programming more predictable because they work like variables in most programming languages.

They allow you to redefine a variable using its own value or its value processed in some way by one of the expansion functions and to use the expansion functions much more efficiently see Functions for Transforming Text.

You can also use them to introduce controlled leading whitespace into variable values. Leading whitespace characters are discarded from your input before substitution of variable references and function calls; this means you can include leading spaces in a variable value by protecting them with variable references, like this:.

Here the value of the variable space is precisely one space. Since trailing space characters are not stripped from variable values, just a space at the end of the line would have the same effect but be rather hard to read.

If you put whitespace at the end of a variable value, it is a good idea to put a comment like that at the end of the line to make your intent clear. Conversely, if you do not want any whitespace characters at the end of your variable value, you must remember not to put a random comment on the end of the line after some whitespace, such as this:.

This is called a conditional variable assignment operator, because it only has an effect if the variable is not yet defined. This section describes some advanced features you can use to reference variables in more flexible ways. Computed NamesPrevious: A substitution reference substitutes the value of a variable with alterations that you specify. A substitution reference is actually an abbreviation for use of the patsubst expansion function see Functions for String Substitution and Analysis.

We provide substitution references as well as patsubst for compatibility with other implementations of make. Another type of substitution reference lets you use the full power of the patsubst function. See Functions for String Substitution and Analysisfor a description of the patsubst function. Substitution RefsUp: Computed variable names are a complicated concept needed only for sophisticated makefile programming.

For most purposes you need not consider them, except to know that making a variable with a dollar sign in its name might have strange results. However, if you are the type that wants to understand everything, or you are actually interested in what they do, read on. Variables may be referenced inside the name of a variable. This is called a computed variable name or a nested variable reference. The previous example shows two levels of nesting, but any number of levels is possible.

For example, here are three levels:. References to recursively-expanded variables within a variable name are re-expanded in the usual fashion. Nested variable references can also contain modified references and function invocations see Functions for Transforming Textjust like any other reference. For example, using the subst function see Functions for String Substitution and Analysis:.

It is doubtful that anyone would ever want to write a nested reference as convoluted as this one, but it works: A computed variable name need not consist entirely of a single variable reference. It can contain several variable references, as well as some invariant text. The only restriction on this sort of use of nested variable references is that they cannot specify part of the name of a function to be called. This is because the test for a recognized function name is done before the expansion of nested references.

This restriction could be removed in the future if that change is shown to be a good idea. You can also use computed variable names in the left-hand side of a variable assignment, or in a define directive, as in:. Note that nested variable references are quite different from recursively expanded variables see The Two Flavors of Variablesthough both are used together in complex ways when doing makefile programming. See The Two Flavors of Variables. The variable name may contain function and variable references, which are expanded when the line is read to find the actual variable name to use.

There is no limit on the length of the value of a variable except the amount of memory on the computer. You can split the value of a variable into multiple physical lines for readability see Splitting Long Lines.

Most variable names are considered to have the empty string as a value if you have never set them. Several variables have built-in initial values that are not empty, but you can set them in the usual ways see Variables Used by Implicit Rules. Several special variables are set automatically to a new value for each rule; these are called the automatic variables see Automatic Variables.

This operator first evaluates the right-hand side, then passes that result to the shell for execution. If the result of the execution ends in a newline, that one newline is removed; all other newlines are replaced by spaces. The resulting string is then placed into the named recursively-expanded variable. Alternatively, you can set a simply expanded variable to the result of running a program using the shell function call.

As with the shell function, the exit status of the just-invoked shell script is stored in the. Override DirectivePrevious: Often it is useful to add more text to the value of a variable already defined. See The Two Flavors of Variablesfor an explanation of the two flavors of variables. Recall that when you define a recursively-expanded variable, make does not expand the value you set for variable and function references immediately.

Instead it stores the text verbatim, and saves these variable and function references to be expanded later, when you refer to the new variable see The Two Flavors of Variables.

Take this common example:. The first line defines the CFLAGS variable with a reference to another variable, includes. CFLAGS is used by the rules for C compilation; see Catalogue of Built-In Rules. Thus, includes need not be defined yet for its value to take effect. It only has to be defined before any reference to CFLAGS. This is pretty close, but not quite what we want.

If a variable has been set with a command argument see Overriding Variablesthen ordinary assignments in the makefile are ignored. If you want to set the variable in the makefile even though it was set with a command argument, you can use an override directive, which is a line that looks like this:. Variable assignments marked with the override flag have a higher priority than all other assignments, except another override. Subsequent assignments or appends to this variable which are not marked override will be ignored.

The override directive was not invented for escalation in the war between makefiles and command arguments. It was invented so you can alter and add to values that the user specifies with command arguments.

You could use this override directive:. You can also use override directives with define directives. This is done as you might expect:. Undefine DirectivePrevious: Override DirectiveUp: Another way to set the value of a variable is to use the define directive.

This directive has an unusual syntax which allows newline characters to be included in the value, which is convenient for defining both canned sequences of commands see Defining Canned Recipesand also sections of makefile syntax to use with eval see Eval Function. The define directive is followed on the same line by the name of the variable being defined and an optional assignment operator, and nothing more.

The value to give the variable appears on the following lines. The end of the value is marked by a line containing just the word endef.

Aside from this difference in syntax, define works just like any other variable definition. The variable name may contain function and variable references, which are expanded when the directive is read to find the actual variable name to use. You may omit the variable assignment operator if you prefer. You may nest define directives: Note that lines beginning with the recipe prefix character are considered part of a recipe, so any define or endef strings appearing on such a line will not be considered make directives.

However, note that using two separate lines means make will invoke the shell twice, running an independent sub-shell for each line.

If you want variable definitions made with define to take precedence over command-line variable definitions, you can use the override directive together with define:. If you want to clear a variable, setting its value to empty is usually sufficient. Expanding such a variable will yield the same result empty string regardless of whether it was set or not.

However, if you are using the flavor see Flavor Function and origin see Origin Function functions, there is a difference between a variable that was never set and a variable with an empty value. In such situations you may want to use the undefine directive to make a variable appear as if it was never set.

If you want to undefine a command-line variable definition, you can use the override directive together with undefinesimilar to how this is done for variable definitions:. Undefine DirectiveUp: Variables in make can come from the environment in which make is run. Every environment variable that make sees when it starts up is transformed into a make variable with the same name and value. However, an explicit assignment in the makefile, or with a command argument, overrides the environment.

But this is not recommended practice. Thus, by setting the variable CFLAGS in your environment, you can cause all C compilations in most makefiles to use the compiler switches you prefer. This is safe for variables with standard or conventional meanings because you know that no makefile will use them for other things. Note this is not totally reliable; some makefiles set CFLAGS explicitly and therefore are not affected by the value in the environment. When make runs a recipe, variables defined in the makefile are placed into the environment of each shell.

This allows you to pass values to sub- make invocations see Recursive Use of make. By default, only variables that came from the environment or the command line are passed to recursive invocations.

You can use the export directive to pass other variables. See Communicating Variables to a Sub- makefor full details. Other use of variables from the environment is not recommended. It is not wise for makefiles to depend for their functioning on environment variables set up outside their control, since this would cause different users to get different results from the same makefile.

This is against the whole purpose of most makefiles. It would be very undesirable for this choice to affect make ; so, make handles the SHELL environment variable in a special way; see Choosing the Shell.

One exception to that is automatic variables see Automatic Variables. The other exception is target-specific variable values. This feature allows you to define different values for the same variable, based on the target that make is currently building. Target-specific variable assignments can be prefixed with any or all of the special keywords exportoverrideor private ; these apply their normal behavior to this instance of the variable only. Multiple target values create a target-specific variable value for each member of the target list individually.

All variables that appear within the variable-assignment are evaluated within the context of the target: Target-specific variables have the same priority as any other makefile variable. Specifying the override directive will allow the target-specific variable value to be preferred. There is one more special feature of target-specific variables: So, for example, a statement like this:. Be aware that a given prerequisite will only be built once per invocation of make, at most.

If the same file is a prerequisite of multiple targets, and each of those targets has a different value for the same target-specific variable, then the first target to be built will cause that prerequisite to be built and the prerequisite will inherit the target-specific value from the first target. It will ignore the target-specific values from any other targets.

Suppressing InheritancePrevious: In addition to target-specific variable values see Target-specific Variable ValuesGNU make supports pattern-specific variable values. In this form, the variable is defined for any target that matches the pattern specified.

As with target-specific variable values, multiple pattern values create a pattern-specific variable value for each pattern individually. The variable-assignment can be any valid form of assignment. Any command line variable setting will take precedence, unless override is specified. If a target matches more than one pattern, the matching pattern-specific variables with longer stems are interpreted first. This results in more specific variables taking precedence over the more generic ones, for example:.

Pattern-specific variables which result in the same stem length are considered in the order in which they were defined in the makefile. Pattern-specific variables are searched after any target-specific variables defined explicitly for that target, and before target-specific variables defined for the parent target.

Special VariablesPrevious: As described in previous sections, make variables are inherited by prerequisites. This capability allows you to modify the behavior of a prerequisite based on which targets caused it to be rebuilt. Sometimes, however, you may not want a variable to be inherited. For these situations, make provides the private modifier. Although this modifier can be used with any variable assignment, it makes the most sense with target- and pattern-specific variables.

Any variable marked private will be visible to its local target but will not be inherited by prerequisites of that target. A global variable marked private will be visible in the global scope but will not be inherited by any target, and hence will not be visible in any recipe. Due to the private modifier, a. Suppressing InheritanceUp: Contains the name of each makefile that is parsed by makein the order in which it was parsed.

The name is appended just before make begins to parse the makefile. Thus, if the first thing a makefile does is examine the last word in this variable, it will be the name of the current makefile.

Once the current makefile has used includehowever, the last word will be the just-included makefile. Sets the default goal to be used if no targets were specified on the command line see Arguments to Specify the Goals. The following example illustrates these cases:. Note that assigning more than one target name to. This variable is set only if this instance of make has restarted see How Makefiles Are Remade: Note this is not the same as recursion counted by the MAKELEVEL variable.

You should not set, modify, or export this variable. When make starts it will check whether stdout and stderr will show their output on a terminal. If set these variables will be marked for export. These variables will not be changed by make and they will not be modified if already set. These values can be used particularly in combination with output synchronization see Output During Parallel Execution to determine whether make itself is writing to a terminal; they can be tested to decide whether to force recipe commands to generate colorized output for example.

If you invoke a sub- make and redirect its stdout or stderr it is your responsibility to reset or unexport these variables as well, if your makefiles rely on them.

The first character of the value of this variable is used as the character make assumes is introducing a recipe line. If the variable is empty as it is by default that character is the standard tab character.

For example, this is a valid makefile:. Expands to a list of the names of all global variables defined so far. This includes variables which have empty values, as well as built-in variables see Variables Used by Implicit Rulesbut does not include any variables which are only defined in a target-specific context.

Note that any value you assign to this variable will be ignored; it will always return its special value. Expands to a list of special features supported by this version of make. Possible values include, but are not limited to:.

Supports ar archive files using special file name syntax. See Using make to Update Archive Files. Supports the -L --check-symlink-times flag.

See Syntax of Conditionals. See Using One Shell. See Types of Prerequisites. See How Patterns Match. Supports target-specific and pattern-specific variable assignments. See Target-specific Variable Values. Supports the undefine directive. Has GNU Guile available as an embedded extension language. See GNU Guile Integration. Supports dynamically loadable objects for creating custom extensions.